Publications:
- Over 100 research papers in reviewed journals and international conferences with citations in US patents and journals.
- h-index: 18 @ Scopus (Author ID: 6701717892)
(a) Technical Reports:
1.
"Junctionless Transistors", A. Kranti, R. Yan and J.-P. Colinge,
Report submitted to Intel Corp., Portland,
(b) Journals (Reviewed):
1. "Influence of elastic-phonon interaction on quantum transport in multi-gate silicon nanowire MOSFETs", N. Akhavan, A. Afzalian, A Kranti, I. Ferain, C.-W. Lee, R. Yan, R. Yu and J.-P. Colinge, IEEE Trans. Electron Devices, vol. 58, no. 4, pp. 1029-1037, 2011.2010.
2. "Junctionless 6T SRAM Cell", A. Kranti, C.-W. Lee, I. Ferain, R. Yan, N. Akhavan, P. Razavi, R. Yu, G.A. Armstrong and J.-P. Colinge, IET Electronics Letters, vol.46, no. 22, pp. 1491-1493, 2010.
3. “Non–Classical Channel Design in MOSFETs for Improving OTA Gain–Bandwidth Trade–off”, A. Kranti and G.A. Armstrong, IEEE Transactions on Circuits and Systems-I, vol. 57, no. 12, pp. 3048-3054, 2010.
4. “Mobility improvement in nanowire Junctionless transistors by uniaxial strain”, J.-P. Raskin, J.-P. Colinge, I. Ferain, A. Kranti, C.-W. Lee, N. Akhavan, R. Yan, P. Razavi and R. Yu, Applied Physics Letters, vol. 97, article no. 042114, 2010.
5. “Impact of gate-source/drain channel architecture on the performance of operational transconductance amplifier (OTA)”, A. Kranti, Rashmi and G.A. Armstrong, Semiconductor Science and Technology, vol. 24, no. 11, article no. 115002, 2009.
6. "How crucial is back gate misalignment/oversize in double gate MOSFETs for ultra-low-voltage analog/RF applications?", A. Kranti and G.A. Armstrong, Solid-State Electronics, vol. 52, no. 12, pp. 1895-1903, 2008.
7. “Improving fMAX/fT ratio in FinFETs using source/drain extension region engineering”, A. Kranti and G.A. Armstrong, Electronics Letters, vol. 44, no. 13, pp. 825-827, 2008.
8. “6-T SRAM cell design with nanoscale double gate SOI MOSFETs: impact of source/drain engineering and circuit topology”, Rashmi, A. Kranti and G.A. Armstrong, Semiconductor Science and Technology, vol. 23, no. 7, article 075049, 2008.
9. “High tolerance to gate misalignment in low voltage gate–underlap double gate MOSFETs”, A. Kranti and G.A. Armstrong, IEEE Electron Device Letters, vol. 29, no. 5, pp. 503-505, 2008.
10. “Performance projections and design optimization of planar double gate SOI MOSFETs for logic technology applications”, A. Kranti, Y. Hao and G.A. Armstrong, Semiconductor Science and Technology, vol. 23, no. 4, article 045001, 2008.
11. “Source/drain extension region engineering in nanoscale double gate SOI MOSFETs: Novel design methodology for low voltage applications”, A. Kranti and G.A. Armstrong, Microelectronic Engineering, vol. 84, no.12, pp. 2775-2784, 2007.
12. “Design and optimization of FinFETs for ultra–low–voltage analog applications”, A. Kranti and G.A. Armstrong, IEEE Transactions on Electron Devices, vol. 54, no.12, pp. 3308-3316, 2007.
13. "Optimization of trench isolated bipolar transistors on SOI substrates by 3D electro-thermal simulations", S. Nigrin, G.A. Armstrong and A. Kranti, Solid-State Electronics, vol. 51, no. 9, pp. 1212-1228, 2007.
14. “Comparative analysis of nanoscale MOS device architectures for RF applications”, A. Kranti and G.A. Armstrong, Semiconductor Science and Technology, vol. 22, no. 5, pp. 481-491, 2007.
15. “Source/Drain Extension Region Engineering in FinFETs for Low-Voltage Analog Applications”, A. Kranti and G.A. Armstrong, IEEE Electron Device Letters, vol. 28, no. 2, pp. 139–141, 2007.
16. “Optimization of source/drain extension region profile for suppression of short channel effects in sub-50 nm DG MOSFET with high–K gate dielectrics”, A. Kranti and G.A. Armstrong, Semiconductor Science and Technology, vol. 21, no. 12, pp. 1563-1572, 2006.
17. "Engineering source/drain extension regions in nanoscale double gate (DG) SOI MOSFETs: analytical model and design considerations", A. Kranti and G.A. Armstrong, Solid-State Electronics, vol. 50, no. 3, pp. 437-447, 2006.
18. “Performance assessment of nanoscale double and triple gate FinFETs”, A. Kranti and G.A. Armstrong, Semiconductor Science and Technology, vol. 21, no. 4, pp. 409-421, 2006.
19. “Gate length scaling and microwave performance of double gate nanotransistors”, A. Kranti, T.M. Chung and J.P. Raskin, International Journal of Nanoscience, vol. 4, no. 5-6, pp. 1021-1024, 2005.
20. “Analysis of quasi double gate method for performance prediction of deep submicron double gate SOI MOSFETs”, A. Kranti, T.M. Chung, D. Flandre and J.P. Raskin, Semiconductor Science and Technology, vol. 20, no. 5, pp. 423-429, 2005.
21. “Analysis of static and dynamic performance of short channel double gate SOI MOSFETs for improved cut-off frequency”, A. Kranti, T.M. Chung and J.P. Raskin, Japanese Journal of Applied Physics, vol. 44, no. 4B, pp. 2340-2346, 2005.
22. “Laterally asymmetric channel engineering in fully depleted double gate SOI MOSFETs for high performance analog applications”, A. Kranti, T.M. Chung, D. Flandre and J.P. Raskin, Solid-State Electronics, vol. 48, no.6, pp. 947-959, 2004.
23. “Modeling of threshold voltage adjustment in fully depleted double gate (DG) SOI MOSFETs in volume inversion to quantify requirements of gate materials”, A. Kranti, Rashmi, S. Haldar and R.S. Gupta, Indian Journal of Pure and Applied Physics, vol. 42 no. 3, pp. 211-220, 2004.
24. “Comprehensive analysis of small signal parameters of fully strained and partially relaxed high Al-content lattice mismatched AlmGa1-mN/GaN HEMTs”, Rashmi, A. Kranti, S. Haldar, M. Gupta and R.S. Gupta, IEEE Trans. Microwave Theory and Techniques, vol. 51, no. 2, pp. 607-617, 2003.
25. “Extraction technique for characterization of electric field distribution and drain current in VDMOS power transistor”, N. Kaushik, A. Kranti, M Gupta and R.S. Gupta, Microelectronics Journal, vol. 34, no. 1, pp. 77-83, 2003.
26. "Design and optimization of vertical surrounding gate (VSG) MOSFETs for enhanced transconductance-to-current ratio (gm/Ids)", A. Kranti, Rashmi, S. Haldar and R.S. Gupta, Solid-State Electronics, vol. 47, no. 1, pp. 155-159, 2003.
27. "Design and optimization of thin film fully depleted vertical surrounding gate (VSG) MOSFETs for enhanced short channel immunity", A. Kranti, Rashmi, S. Haldar and R.S. Gupta, Solid-State Electronics, vol. 46, no.9, pp. 1333-1338, 2002.
28. "An accurate charge control model for spontaneous and piezoelectric polarization dependent two-dimensional electron gas (2-DEG) sheet charge density of lattice mismatched AlGaN/GaN HEMTs", Rashmi, A. Kranti, S. Haldar and R.S. Gupta, Solid-State Electronics, vol. 46, no. 5, pp. 621-630, 2002.
29. “Impact of strain relaxation of AlmGa1-mN layer on 2-DEG sheet charge density and current voltage characteristics of lattice mismatched AlmGa1-mN/GaN HEMTs”, Rashmi, A. Kranti, S. Haldar and R.S. Gupta, Microelectronics Journal, vol. 33, no. 3, pp. 205-212, 2002.
30. “An accurate two-dimensional CAD oriented model of retrograde doped MOSFETs for improved short channel performance”, A. Kranti, Rashmi, S. Haldar and R.S. Gupta, Microelectronic Engineering, vol. 60, no. 3-4, pp. 295-311, 2002.
31. “An accurate 2-D model for transconductance-to-current ratio and drain conductance of vertical surrounding gate (VSG) MOSFETs for microwave circuits applications”, A. Kranti, Rashmi, S. Haldar and R.S. Gupta, Microwave and Optical Technology Letters, vol. 31, no. 6, pp. 415-421, 2002.
32. “An analytical model for threshold voltage and I-V characteristics of fully depleted short channel cylindrical/surrounding gate MOSFET”, A. Kranti, S. Haldar and R.S. Gupta, Microelectronic Engineering, vol. 56, no. 3-4, pp. 241-259, 2001.
33. “Optimization for improved short channel performance of surrounding/cylindrical gate (SGT) MOSFETs”, A. Kranti, Rashmi, S. Haldar and R.S. Gupta, Electronics Letters, vol. 37, no. 8, pp. 533-534, 2001.
34. “An accurate 2-D analytical model for short channel thin film fully depleted cylindrical/surrounding gate (CGT/SGT) MOSFET”, A. Kranti, S. Haldar and R.S. Gupta, Microelectronics Journal, vol. 32, no. 4, pp. 305-313, 2001.
35. “An analytical 2-dimensional model for optically controlled thin film fully depleted surrounding/cylindrical gate (SGT/CGT) MOSFET”, A. Kranti, S. Haldar and R.S. Gupta, Microwave and Optical Technology Letters, vol. 28, no. 2, pp. 135-141, 2001.
36. “Temperature dependent threshold voltage analysis of surrounding/cylindrical gate fully depleted thin film SOI MOSFET in the range 77 to 520K”, A. Kranti, S. Haldar and R.S. Gupta, Microelectronic Engineering, vol. 49, no. 3-4, pp. 273-286, 1999.
(c) International Conferences (Reviewed):
1. "Source/Drain engineered ultra low power analog/RF UTBB MOSFET", A. Kranti, J.-P. Raskin and G.A. Armstrong, In Proc. Ultimate Integration on Silicon (ULIS), Ireland, Digital Object Identifier: 10.1109/ULIS.2011.5757997, 2011.
2. “Extraction of flat-band voltage and parasitic resistance in junctionless MuGFETs”, A.N. Nazarov, C.W. Lee, A. Kranti, I. Ferain, R. Yan, N. Dehdashti Akhavan, P. Razavi, R. Yu, JP Colinge, In Proc. Seventh Workshop of the Thematic Network on Silicon on Insulator Technology, Devices and Circuits (EuroSOI 2011), Spain, pp. 53-54, 2011.
3. "A simulation comparison between junctionless and inversion-mode MuGFETs", J.P. Colinge, A. Kranti, R. Yan, I. Ferain, N. Akhavan, P. Razavi, C.W. Lee, R. Yu and C.A. Colinge, 219 ECS Meeting: Advanced Silicon-on-Insulator Technology and Related Physics, In Proc. ECS Transactions, vol. 35, no. 5, Eds. Y. Omura, F. Gamiz, H. Ishii, J.A. Martino, B.-Y. Nguyen, J.-P. Raskin and S. Selberherr, pp. 63-72, 2011.
4. "Comparative study of random telegraph noise in junctionless and inversion-mode MuGFETs", A.N. Nazarov, C.W. Lee, A. Kranti, I. Ferain, R. Yan, N. Akhavan, P. Razavi, R. Yu, J.P. Colinge, 219 ECS Meeting: Advanced Silicon-on-Insulator Technology and Related Physics, In Proc. ECS Transactions, vol. 35, no. 5, Eds. Y. Omura, F. Gamiz, H. Ishii, J.A. Martino, B.-Y. Nguyen, J.-P. Raskin and S. Selberherr, pp. 73-78, 2011.
5. “Extraction of channel mobility in nanowire MOSFETs using Id(Vg) characteristics and random telegraph noise amplitude”, A.N. Nazarov, C.W. Lee, A. Kranti, I. Ferain, R. Yan, N. Akhavan, P. Razavi, R. Yu and J.-P. Colinge, In Proc. Ultimate Integration on Silicon (ULIS), Ireland, Digital Object Identifier: 10.1109/ULIS.2011.5757991, 2011.
6. “Junctionless Nanowire Transistor (JNT): Properties and Design Guidelines”, A. Kranti, R. Yan, C.-W. Lee, I. Ferain, R. Yu, N. Dehdashti Akhavan, P. Razavi, J.-P. Colinge, In Proc. European Solid State Device Research Conference (ESSDERC), pp. 357-360, 2010.
7. “Analysis of Junctionless Transistor Architecture”, J.-P. Colinge, J.-P. Raskin, A. Kranti, I. Ferain, C.-W. Lee, N. Dehdashti Akhavan, P. Razavi, R. Yan and R. Yu, In Abs. Solid-State Devices and Materials (SSDM) Conference, Japan, paper C-9-4, 2010.
8. “Characterization of junctionless Z-RAM cell”, C.-W. Lee, S. Okhonin, M. Nagoya, A. Kranti, I. Ferain, N. Dehdashti Akhavan, P. Razavi, R. Yu, R. Yan and J.-P. Colinge, In Abs. Solid-State Devices and Materials (SSDM) Conference, Japan, paper E-1-2, 2010.
9. "Short channel junctionless nanowire transistors", C.-W. Lee, I. Ferain, A. Kranti, N. Dehdashti Akhavan, P. Razavi, R. Yan, R. Yu, B. O’Neill, A. Blake, M. White, A.M. Kelleher, B. McCarthy, S. Gheorghe, R. Murphy and J.-P. Colinge, In Abs. Solid-State Devices and Materials (SSDM) Conference, Japan, paper C-9-5, 2010.
10. "Dissipative transport in Multigate silicon nanowire transistors", N. Dehdashti, A. Kranti, I. Ferain, C.-W. Lee; R. Yan, P. Razavi, R. Yu, J.-P. Colinge, In Proc. International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Italy, pp. 97-100, 2010.
11. “Analysis of Junctionless Transistor Architecture”, J.-P. Colinge, J.-P. Raskin, A. Kranti, I. Ferain, C.-W. Lee, N. Dehdashti Akhavan, P. Razavi, R. Yan and R. Yu, In Abs. Solid-State Devices and Materials (SSDM) Conference, Japan, paper C-9-4, 2010.
12. “Characterization of junctionless Z-RAM cell”, C.-W. Lee, S. Okhonin, M. Nagoya, A. Kranti, I. Ferain, N. Dehdashti Akhavan, P. Razavi, R. Yu, R. Yan and J.-P. Colinge, In Abs. Solid-State Devices and Materials (SSDM) Conference, Japan, paper E-1-2, 2010.
13. "Short-Channel Junctionless Nanowire Transistors", C.-W. Lee, I. Ferain, A. Kranti, N. Dehdashti Akhavan, P. Razavi, R. Yan, R. Yu, B. O’Neill, A. Blake, M. White, A.M. Kelleher, B. McCarthy, S. Gheorghe, R. Murphy and J.-P. Colinge, In Abs. Solid-State Devices and Materials (SSDM) Conference, Japan, paper C-9-5, 2010.
14. "Dissipative transport in Multigate silicon nanowire transistors", N. Dehdashti, A. Kranti, I. Ferain, C.-W. Lee; R. Yan, P. Razavi, R. Yu, J.-P. Colinge, In Proc. International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Italy, pp. 97-100, 2010.
15. "Emission and absorption of optical phonons in multigate silicon nanowire MOSFETs", N. Dehdashti, A. Kranti, I. Ferain, C.-W. Lee, R. Yan, P. Razavi, R. Yu and J.-P. Colinge, In Proc. International Workshop on Computational Electronics (IWCE), DOI: 10.1109/IWCE.2010.5677915 , 2010.
16. "Mobility improvement in nanowire junctionless transistors by uniaxial strain", J.-P. Raskin, J.-P. Colinge, I. Ferain, A. Kranti, C.-W. Lee, N. Dehdashti, R. Yan, P. Razavi and R. Yu, In Proc. IEEE International SOI Conference, USA, Digital Object Identifier: 10.1109/SOI.2010.5641390, 2010.
17. "Analog operation of junctionless transistors at cryogenic temperatures", R.T. Doria, M.A. Pavanello, R.D. Trevisoli, M de Souza, C.-W. Lee Lee, I. Ferain, N. Dehdashti Akhavan, R. Yan, P. Razavi, R. Yu, A. Kranti and J.-P. Colinge, In Proc. IEEE International SOI Conference, USA, Digital Object Identifier: 10.1109/SOI.2010.5641393, 2010.
18. "Nanowire zero-capacitor DRAM transistors with and without junctions", C.-W. Lee, R. Yan, I. Ferain, A. Kranti, N. Dehdashti Akhvan, P. Razavi, R. Yu, J.-P. Colinge, IEEE Conference on Nanotechnology (IEEE-NANO), Korea, pp. 242-245, DOI: 10.1109/NANO.2010.5697888, 2010.
19. “Analog/RF performance of sub–100 nm SOI MOSFETs with non–classical gate–source/drain underlap channel design”, A. Kranti, Rashmi, S. Burignat, J.-P. Raskin and G.A. Armstrong, Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), pp. 45-48, 2010.
20. “High temperature performance of OTA with non–ideal double gate SOI MOSFETs”, A. Kranti and G.A. Armstrong, 2009 IEEE SOI Conference, pp. 153-154, 2009.
21. “Improving operational transconductance amplifier (OTA) gain-bandwidth tradeoff using gate-underlap MOSFETs”, A. Kranti and G.A. Armstrong, IEEE System on Chip Conference (SOCC), pp. 107-110, 2009.
22. “Underlap channel UTBB MOSFETs for low-power analog/RF applications”, A. Kranti, S. Burignat, J.-P. Raskin and G.A. Armstrong, In Proc. European Workshop on Ultimate Integration of Silicon (ULIS), pp. 173-176, 2009.
23. “Optimizing spacer–to–straggle ratio in gate underlap SOI MOSFETs for low voltage analog and digital circuits”, A. Kranti, Rashmi and G.A. Armstrong, 215th Electrochemical Society Meeting, In Proc. ECS Transactions (SOI Device Technology), vol. 19, no. 4, pp. 283-288, 2009.
24. “Thermal resistance model for multi-finger trench-isolated Bipolar transistors on SOI substrate”, Rashmi, A. Kranti, G.A. Armstrong and S. Nigrin, 215th Electrochemical Society Meeting, In Proc. ECS Transactions (SOI Device Technology), vol. 19, no. 4, pp. 305-310, 2009.
25. “Optimizing FinFET geometry and parasitics for RF applications”, A. Kranti, J.-P. Raskin and G.A. Armstrong, 2008 IEEE SOI Conference, pp. 123-124, 2008.
26. “Insights into gate–underlap design in double gate based 6–T SRAM cell for low voltage applications”, Rashmi, A. Kranti and G.A. Armstrong, 2008 IEEE SOI Conference, pp. 61-62, 2008.
27. “How crucial is gate misalignment for low–voltage operation in double gate SOI MOSFETs?”, A. Kranti and G.A. Armstrong, In Proc. Fourth Workshop of the Thematic Network on Silicon on Insulator technology, devices and circuits (EuroSOI 2008), Cork, Ireland, pp. 133-134, 2008.
28. “Influence of gate–underlap design on the performance of 6T–SRAM cell with double gate SOI MOSFETs”, Rashmi, A. Kranti and G.A. Armstrong, In Proc. Fourth Workshop of the Thematic Network on Silicon on Insulator technology, devices and circuits (EuroSOI 2008), Cork, Ireland, pp. 23-24, 2008.
29. “Insights into gate–underlap design in FinFETs for ultra–low voltage analog performance”, A. Kranti and G.A. Armstrong, 2007 IEEE SOI Conference, pp. 33-34, 2007.
30. “Significance of gate underlap architecture in FinFETs for low–voltage analog/RF applications”, A. Kranti and G.A. Armstrong, 211th Electrochemical Society Meeting (Chicago, USA), In Proc. ECS Transactions (SOI Device Technology), vol. 6, no. 4, pp. 375-380, 2007.
31. “3D electro-thermal simulations of trench isolated bipolar transistors on SOI substrates”, G.A. Armstrong, A. Kranti and S. Nigrin, In Proc. Third Workshop of the Thematic Network on Silicon on Insulator technology, devices and circuits (EuroSOI 2007), Leuven, Belgium, pp. 58-59, 2007.
32. “Source/Drain extension region engineering in nanoscale double gate SOI MOSFETs for low voltage analog applications”, A. Kranti, T.C. Lim and G.A. Armstrong, 2006 IEEE SOI Conference, Niagara Falls, USA, pp. 141-142, 2006.
33. “Performance assessment of nanoscale multiple gate MOSFETs (MuGFETs) for RF applications”, T.C. Lim, A. Kranti and G.A. Armstrong, European Microwave Integrated Circuits (EuMIC) Conference 2006, Manchester, UK, pp. 308-311, 2006.
34. “On the feasibility of nanoscale FinFETs for RF
applications”, A. Kranti and G.A. Armstrong, 2006 Silicon Nanoelectronics Workshop,
35. “Optimal design of source/drain extension (SDE) regions in multiple gate MOSFETs”, A. Kranti and G.A. Armstrong, In Proc. Seventh European Workshop on Ultimate Integration of Silicon (ULIS) 2006, Grenoble, France, pp. 137-140, 2006.
36. “Modelling short channel effects in source/drain extension region engineered double gate MOSFETs”, A. Kranti and G.A. Armstrong, In Proc. Second Workshop of the Thematic Network on Silicon on Insulator Technology EuroSOI 2006, Grenoble, France, pp. 131-132, 2006.
37. “Compact model for short channel effects in source/drain engineered nanoscale double gate (DG) SOI MOSFETs, A. Kranti and G.A. Armstrong, 2006 Workshop on Compact Modeling – NSTI Nanotech 2006, Boston, USA, pp. 820-823, 2006.
38. “Device design considerations for nanoscale double and triple gate FinFETs”, A. Kranti and G.A. Armstrong, In Proc. IEEE SOI Conference, Honolulu, Hawaii, USA, pp. 96-98, 2005.
39. “2-D and 3-D wideband simulations of multiple-gate SOI MOSFETs”, T.M. Chung, A. Kranti and J.-P. Raskin, In Proc. 6th European Conference on Ultimate Integration of Silicon (ULIS), Bologna, Italy, pp. 83-86, 2005.
40. “3-D simulations of multiple-gate SOI MOSFETs in static and dynamic regimes” T. M. Chung, A. Kranti and J.-P. Raskin, In Abs. First Workshop of the Thematic Network on Silicon on Insulator Technology – EuroSOI 2005, Devices and Circuits, Granada, Spain, pp. 73-74, 2005.
41. “Double gate SOI devices for analog applications”, A. Kranti and J.-P. Raskin, In Abs. Asia Pacific Microwave Conference, New Delhi, India, pp. 185-186, 2004.
42. “Double Gate SOI MOSFET – considerations for improved cut-off frequency”, A. Kranti, T. M. Chung and J.-P. Raskin, In Abs. 2004 International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, pp. 784-785, 2004.
43. “Gate length scaling and microwave performance of double gate nano-transistors”, A. Kranti, T. M. Chung and J.-P. Raskin, In Abs. International Conference on Nano Science and Technology (ICONSAT), Kolkata, India, pp. 88, 2003.
44. “Operation of double gate graded-channel transistors at
low temperatures", J. A. Martino, M. A. Pavanello, T.M. Chung, A. Kranti,
J.-P. Raskin and D. Flandre, In Abs. The Electrochemical Society Conference, Orlando,
45. “Analysis of laterally asymmetric channel design in fully depleted double gate (DG) SOI MOSFETs for high performance analog applications”, A. Kranti, T.M. Chung, D. Flandre and J.-P. Raskin, In Proc. European Solid-State Device Research Conference (ESSDERC), Estoril, Portugal, pp. 131-134, 2003.
46. “Impact of the graded-channel architecture on double gate transistors for high-performance analog applications”, M. A. Pavanello, J. A. Martino, T.M. Chung, A. Kranti, J.-P. Raskin and D. Flandre, In Proc. The Electrochemical Society Conference, Paris, France, pp. 261-266, 2003.
47. “Modeling of AlxGa1-xN/GaN heterostructure field effect transistors (HFETs) for microwave and millimeter wave applications”, R.S. Gupta, Rashmi, A. Kranti and S. Haldar, In Proc. Eleventh International Workshop on Physics of Semiconductor Devices, New Delhi, India, vol., 2, pp. 819-826, 2001.
48. “Threshold voltage model for short channel retrograde doped MOSFETs”, A. Kranti, Rashmi, S. Haldar and R.S. Gupta, In Proc. Eleventh International Workshop on Physics of Semiconductor Devices, New Delhi, India, vol. 1, pp. 672-676, 2001.
49. “A physics based charge control model of lattice mismatched AlGaN/GaN HEMTs”, Rashmi, A. Kranti, S. Haldar and R.S. Gupta, In Proc. Eleventh International Workshop on Physics of Semiconductor Devices, New Delhi, India, vol. 2, pp. 911-914, 2001.
50. “Design guidelines of vertical surrounding gate (VSG) MOSFETs for future ULSI circuit applications”, A. Kranti, Rashmi, S. Haldar and R.S. Gupta, In Proc. Topical meeting on silicon monolithic integrated circuits in RF systems, Ann Arbor, Michigan, U.S.A., pp. 161-165, 2001.
51. “Piezoelectric polarization dependent model for AlGaN/GaN high electron mobility transistors for improved microwave performance”, Rashmi, A. Kranti, S. Haldar and R.S. Gupta, In Proc. Asia Pacific Microwave Conference 2001, Taipei, Taiwan, R.O.C., pp. 256-259, 2001.
52. “An analytical model for optically controlled fully depleted cylindrical/surrounding gate (CGT/SGT) MOSFET”, A. Kranti, S. Haldar and R.S. Gupta, In Proc. International Conference on Fiber Optics and Photonics-2000, Calcutta, India, vol. 2, pp. 590-592, 2000.
53. “A two-dimensional analytical model for thin film fully depleted surrounded gate (SGT) MOSFET”, A. Kranti, S. Haldar and R.S. Gupta, In Proc. Asia Pacific Microwave Conference, Sydney, Australia, pp. 880-883, 2000.
54. “Analytical temperature dependent threshold voltage for thin film surrounded gate SOI MOSFET”, A. Kranti, S. Haldar and R.S. Gupta, In Proc. Tenth International workshop on the Physics of Semiconductor Devices, New Delhi, India, vol. 1, pp. 605-608, 1999.
55. “Analytical modeling of threshold voltage and drain current in short channel fully depleted cylindrical gate MOSFET”, R.S. Gupta, A. Kranti, and S. Haldar, In Proc. International workshop on the Physics of Semiconductor Devices, New Delhi, India, vol. 1, pp. 475-482, 1999.