Research Highlights:
We have analyzed hysteresis and bipolar effects in unipolar junctionless transistors. It is shown that a change in subthreshold drain current by 5 orders of magnitude can be achieved at a drain voltage of 2.25 V in silicon junctionless transistors. Contrary to the conventional theory, increasing gate oxide thickness results in reduction of subthreshold slope and an increase in drain current, due to bipolar effects.
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2. Low Power Analog/RF Operation of Junctionless MOSFETs:
The usefulness of ultra low power (ULP) junctionless (JL) MOSFETs in achieving improved analog/RF metrics as compared to non-underlap and underlap MOSFETs is demonstrated. At lower values of drain current, JL devices achieve two times higher values of cutoff frequency and maximum oscillation frequency along with 65% improvement in voltage gain in comparison to conventional non-underlap MOSFETs. ULP JL devices, which do not require source/drain (S/D) profile optimization, can perform comparably to underlap devices, thereby relaxing the stringent process constraints associated with S/D profile optimization in nanoscale devices.
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3. Bipolar Snapback for Capacitorless DRAM:
The bipolar snapback effect is analyzed and effective bipolar gain has been extracted in junctionless transistors. The occurrence of snapback at relatively lower drain bias in junctionless MOSFETs in comparison to conventional inversion mode transistors demonstrates the enormous potential for static power reduction in capacitorless dynamic random access memories.
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The single transistor latch phenomenon in junctionless transistors is reported. In the latch condition, the device is unable to turn-off despite a reduction in gate bias. It is shown that impact ionization induced latch condition can occur due to an increase in drain bias, silicon film thickness, gate oxide thickness, and doping concentration. The latch phenomenon is explained in terms of generation–recombination rates, electrostatic potential, electric field distribution and product of current density and electric field (J.E).
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Our work reports the occurrence of Zero Gate Oxide Thickness Coefficient (ZToxC) in junctionless transistors. It is shown that due to bipolar effects, drain current increases with increase in oxide thickness up to a certain gate voltage, whereas, beyond this voltage, drain current follows the conventional theory and reduces with an increase in oxide thickness. The occurrence of ZToxC classifies the predominant conduction mechanism into bipolar or unipolar mode in junctionless devices.
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The potential of junctionless (JL) MOS transistors for ultra low power (ULP) subthreshold logic applications has been evaluated. It is demonstrated that double gate (DG) JL devices, which do not require source or drain extension region engineering, can perform significantly better than conventional inversion mode devices, and comparable with underlap DG MOSFETs for ULP applications. Sensitivity analysis shows that among all device parameters, JL devices exhibit least sensitivity to gate length in comparison with inversion mode and underlap MOSFETs. Results highlight the advantages and challenges of JL transistors for next-generation ULP CMOS logic devices. in junctionless devices.
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The requirement of higher channel doping in low power junctionless transistors is evaluated in this work. It is shown that moderately doped ultra low power junctionless transistors achieve higher performance metrics, lower parameter sensitivity and lower gate workfunction values. The conduction channel is not confined at the center of the film but is spread out across the film. The use of moderately doped channel region requires the careful optimization of the heavily doped source/drain extension regions. A 6T-SRAM cell designed with optimized junctionless devices shows improved Static Noise Margin and write-ability current.
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Back bias induced dynamic and steep subthreshold swing in asymmetric mode junctionless transistors is analyzed. The ratio of electron and hole concentration as a critical parameter for achieving steep sub-60 mV/decade subthreshold swing and the variation in the location of the conducting channel with applied gate voltages is evaluated. It is shown that asymmetric biasing can lead to impact ionization at sub-bandgap voltages.
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The work focuses on the optimization of channel doping and spacer width for enhancing analog/RF performance metrics at low current levels. It is shown that optimum doping and spacer width can enhance cut-off frequency and maximum frequency of oscillation by 40% and intrinsic voltage gain by 15% at very low values of drain current. Gain-bandwidth trade-off can be considerably improved by operating around the analog sweet spot.
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10. Junctionless Transistors for Biosensing Applications:
The potential of double gate junctionless transistors for enhanced sensitivity for detecting biomolecules in cavity modulated field effect transistors (FETs) is demonstrated. The higher values of body factor, achieved in asymmetric gate operation under impact ionization is utilized for enhanced sensing margin which is five times higher than symmetric mode operation. The intrinsic sensitivity is evaluated in terms of threshold voltage change, and the ratio of drain current in presence and absence of biomolecules in JL nanotransistors. It is shown that asymmetric mode junctionless transistor achieves a higher degree of detection sensitivity even for a partially filled cavity.
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